The development of VLSI semi-conductor devices of the Dynamic Random Access Memory (DRAM) type is well known. Over the years, the industry has steadily progressed from DRAMS of the 16K type (as shown in the U.S. Pat. No. 4,081,701 issued to White, McAdams and Redwine), to DRAMS of the 64K type (as shown in U.S. Pat. No. 4,055,444 issued to Rao) to DRAMS of the IMB type (as shown in U.S. Pat. No. 4,658,377 issued McElroy), and progressed to DRAMS of the 4 MB type. The 16 MB DRAM, wherein more than 16 million memory cells are contained on a single semiconductor chip is the next generation of DRAMs scheduled for production.
In designing VLSI semiconductor memory devices of the 16 MB DRAM type, designers are faced with numerous challenges. One area of concern is power consumption. The device must be able to power the increased memory cells and the supporting circuits. However, for commercial viability, the device must not use excessive power. The power supplies used and the burn in voltage for the part must also be compatible with the thin gate oxides in the device.
Another area of concern is the elimination of defects. The development of larger DRAMS has been fostered by the reduction in memory cell geometries, as illustrated in U.S. Pat. No. 4,240,092 to KUO (a planar capacitor cell) and as illustrated in U.S. Pat. No. 4,721,987 to Baglee et. al. (a trench capacitor cell). The extremely small geometries of the 16 MB DRAM will be manufactured using sub-micron technology. The reduction in feature size has meant that particles that previously did not cause problems in the fabrication process, now can cause circuit defects and device failures.
In order to ameliorate defects, redundancy schemes have been introduced. The redundancy schemes normally consist of a few extra rows and columns f memory cells that are placed within the memory array to replace defective rows and columns of memory cells. Designers need new and improved redundancy schemes in order to effectively and efficiently repair defects and thereby increase yields of 16 MB DRAM chips.
Another area of concern is testing. The device must have circuits to allow for the industry standards 16 X parallel tests. In addition, other circuits and test schemes are needed for internal production use to verify operability and reliability.
The options that the device should have is another cause for concern. For instance, some customers require a X1 device, while others require a X4 device. Some require an enhanced page mode of operation. Additionally, it is yet undecided whether the DRAM industry will maintain 4096-cycle refresh, or move towards a lower number of refresh cycles.
Another cause for concern is the physical layout of the chip. The memory cells and supporting circuits must fit on a semiconductor chip of reasonable size. The size of the packaged device must be acceptable to buyers.
New design strategies and circuits are required to meet the above concerns, and other concerns, relating to the development of the next generation, and to future generations, of Dynamic Random Access Memory devices.
It is an object of this invention therefore, to provide a method such that during testing of the memory devices it can easily be determined if the devices remain in the stress test.
Other objects and advantages of this invention will become apparent to those of ordinary skill in the art, having reference to the following specification, together with the drawings.